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10-Bit, 105 MSPS Dual A/D Converter AD9216
FEATURES
Integrated dual 10-bit ADC Single 3 V supply operation (2.85 V to 3.15 V) SNR = 57 dBc (to Nyquist, AD9216-105) SFDR = 75 dBc (to Nyquist, AD9216-105) Low power: 300 mW at 105 MSPS Differential input with 300 MHz 3 dB bandwidth Exceptional crosstalk immunity > 80 dB Offset binary or twos complement data format Clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
AVDD VIN+_A SHA VIN-_A ADC AGND 10 OUTPUT MUX/ BUFFERS 10
D9_A-D0_A OEB_A
REFT_A REFB_A VREF SENSE CLOCK DUTY CYCLE STABILIZER
MUX_SELECT CLK_A CLK_B DCS SHARED_REF
APPLICATIONS
Ultrasound equipment IF sampling in communications receivers 3G, radio point-to-point, LMDS, MMDS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes
AGND
0.5V MODE CONTROL
PWDN_A PWDN_B DFS
REFT_B REFB_B VIN+_B SHA VIN-_B ADC 10 OUTPUT 10 MUX/ BUFFERS
D9_B-D0_B OEB_B
04775-001
AD9216
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and hold amplifiers (SHAs) and an integrated voltage reference. The AD9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 105 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of userselectable input ranges and offsets, including single-ended applications. The AD9216 is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9216 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format.
DRVDD DRGND
Figure 1.
Fabricated on an advanced CMOS process, the AD9216 is available in a space saving, Pb-free, 64-lead LFCSP (9 mm x 9 mm) and is specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/ 65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/ 65 MSPS ADC. 2. 105 MSPS capability allows for demanding high frequency applications. 3. Low power consumption: AD9216-105: 105 MSPS = 300 mW. 4. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be configured for single-ended or differential operation. 5. Typical channel crosstalk of > 80 dB @ fIN up to 70 MHz. 6. The clock duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9216 TABLE OF CONTENTS
DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Logic Specifications.......................................................................... 6 Switching Specifications .................................................................. 7 Timing Diagram ............................................................................... 8 Absolute Maximum Ratings............................................................ 9 Explanation of Test Levels........................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Terminology .................................................................................... 12 Typical Performance Characteristics ........................................... 14 Equivalent Circuits ......................................................................... 18 Theory of Operation ...................................................................... 19 Analog Input ............................................................................... 19 Clock Input and Considerations .............................................. 20 Power Dissipation and Standby Mode..................................... 21 Digital Outputs ........................................................................... 21 Output Coding............................................................................ 22 Timing ......................................................................................... 22 Data Format ................................................................................ 22 Voltage Reference....................................................................... 23 Dual ADC LFCSP PCB.................................................................. 25 Power Connector........................................................................ 25 Analog Inputs.............................................................................. 25 Optional Operational Amplifier............................................... 25 Clock ............................................................................................ 25 Voltage Reference ....................................................................... 25 Data Outputs............................................................................... 25 LFCSP Evaluation Board Bill of Materials (BOM) ................ 26 LFCSP PCB Schematics............................................................. 27 LFCSP PCB Layers ..................................................................... 30 Thermal Considerations............................................................ 35 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD9216 DC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = -0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error1 Reference Voltage INTERNAL VOLTAGE REFERENCE Output Voltage Error Load Regulation @ 1.0 mA INPUT REFERRED NOISE Input Span = 2.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD4 IDRVDD4 PSRR POWER CONSUMPTION PAVDD4 PDRVDD4 Standby Power5 MATCHING CHARACTERISTICS Offset Matching Error6 Gain Matching Error (Shared Reference Mode) Gain Matching Error (Nonshared Reference Mode) Temp Full Full Full 25C Full 25C Full 25C Full Full Full Full 25C 25C Full Full Full Test Level VI VI VI VI V I V I V V V VI V V IV V V Min 10 AD9216BCPZ-105 Typ Max Unit Bits
-3.6 -1.6 -1.0 -0.65 -2.8 -1.8
Guaranteed 0.7 +3.6 0.7 +1.6 0.5 +1.66 0.5 +1.0 1.0 +2.8 1.0 +1.8 10 75 15 2 1.0 0.5 2 2 7 35
% FSR % FSR LSB LSB LSB LSB V/C ppm/C ppm/C mV mV LSB rms V p-p pF k
Full Full Full Full Full 25C 25C 25C 25C 25C 25C
IV IV VI VI V I V V I I I
2.85 2.85
3.0 3.0 100 24 0.1 300 72 3.0
3.15 3.15 110
V V mA mA % FSR mW mW mW % FSR % FSR % FSR
330
-6.0 -0.6 -1.6
1.0 0.1 0.3
+6.0 +0.6 +1.6
1 2
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). Measured with low frequency ramp at maximum clock rate. 3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 24 for the equivalent analog input structure. 4 Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND). 6 Shared reference mode or nonshared reference mode.
Rev. 0 | Page 3 of 36
AD9216 AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = -0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 2.
Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz WORST OTHER (EXCLUDING SECOND OR THIRD) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz fINPUT = 50 MHz fINPUT = 69 MHz fINPUT = 100 MHz Temp Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Test Level IV I IV I V V IV I IV I V V IV I IV I V V IV I IV I V V IV I IV I V V IV I IV I V V 64.6 66.0 58.4 63.0 Min 55.0 56.6 54.8 56.4 AD9216BCPZ-105 Typ Max 57.8 57.8 57.6 57.6 57.4 57.3 57.7 57.7 57.4 57.4 56.8 56.7 9.4 9.4 9.3 9.3 9.2 9.2 -76.0 -76.0 -74.0 -74.0 -74.0 -74.0 -75.0 -75.0 -75.0 -75.0 -77.0 -77.0 75.0 75.0 74.0 74.0 74.0 74.0 -64.6 -68.0 -58.4 -65.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
54.9 56.5 54.3 56.1
8.9 9.2 8.8 9.1
-65.0 -66.0 -62.0 -63.0
Rev. 0 | Page 4 of 36
AD9216
Parameter TWO-TONE SFDR (AIN = -7 dBFS) fIN1 = 69.1 MHz, fIN2 = 70.1 MHz fIN1 = 100.1 MHz, fIN2 = 101.1 MHz ANALOG BANDWIDTH CROSSTALK Temp 25C 25C 25C 25C Test Level V V V V Min AD9216BCPZ-105 Typ Max 70 69 300 -80.0 Unit dBc dBc MHz dB
Rev. 0 | Page 5 of 36
AD9216 LOGIC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = -0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 3.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 DRVDD = 3.0 V High Level Output Voltage Low Level Output Voltage Temp Full Full Full Full Full Test Level IV IV IV IV IV Min 2.0 -10 -10 2 0.8 +10 +10 AD9216BCPZ-105 Typ Max Unit V V A A pF
Full Full
IV IV
2.95 0.05
V V
1
Output voltage levels measured with 5 pF load on each output.
Rev. 0 | Page 6 of 36
AD9216 SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = -0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 4.
Parameter SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate CLK Period OUTPUT PARAMETERS1 Output Propagation Delay2 (tPD) Valid Time3 (tV) Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) Output Enable Time4 Output Disable Time4 Pipeline Delay (Latency) APERTURE Aperture Delay (tA) Aperture Uncertainty (tJ) Wake-Up Time5 OUT-OF-RANGE RECOVERY TIME Temp Full Full Full 25C 25C 25C 25C 25C 25C Full Full Full Full Full Test Level VI V V I I V V V V V V V V V Min 105 10 9.5 3.75 2.0 1.0 1.0 1 1 6 1.5 0.5 7 1 ns ns Cycle Cycle Cycles ns ps rms ms Cycle 4.6 AD9216BCPZ-105 Typ Max Unit MSPS MSPS ns ns
1 2 3
CLOAD equals 5 pF maximum for all output switching parameters. Output delay is measured from clock 50% transition to data 50% transition. Valid time is approximately equal to the minimum output propagation delay. 4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective channel outputs going into high impedance. 5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 F and 10 F capacitors on REFT and REFB.
Rev. 0 | Page 7 of 36
AD9216 TIMING DIAGRAM
N N+1 N+2 N-1 N+3 N+4 N+5 N+6 N+7 N+8
tA
ANALOG INPUT
CLK
tPD
Figure 2.
Rev. 0 | Page 8 of 36
04775-002
DATA OUT
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
AD9216 ABSOLUTE MAXIMUM RATINGS
Table 5.1
Parameter Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF OEB, DFS VINA, VINB VREF SENSE REFB, REFT PDWN ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature With Respect To AGND DRGND DRGND DRVDD DRGND AGND AGND AGND AGND AGND AGND Min -0.3 -0.3 -0.3 -3.9 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -45 Rating Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150 Unit V V V V V V V V V V V C C C C
-65
1
2
Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. Typical thermal impedances (64-lead LFCSP); JA = 26.4C/W. These measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS
Table 6.
Test Level I II III IV V VI Description 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 9 of 36
AD9216 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD CLK_A SHARED_REF MUX_SELECT PDWN_A OEB_A DNC D9_A (MSB) D8_A D7_A D6_A DRGND DRVDD D5_A D4_A D3_A
AGND VIN+_A VIN-_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN-_B VIN+_B AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1 INDICATOR
AD9216
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D2_A D1_A D0_A (LSB) DNC DNC DNC DNC DRVDD DRGND DNC D9_B (MSB) D8_B D7_B D6_B D5_B D4_B
AVDD CLK_B DCS DFS PDWN_B OEB_B DNC DNC DNC DNC D0_B (LSB) DRGND DRVDD D1_B D2_B D3_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC = DO NOT CONNECT
Figure 3. Pin Configuration
Rev. 0 | Page 10 of 36
04775-003
AD9216
Table 7. Pin Function Descriptions
Pin No. 1, 4, 13, 16 2 3 5, 12, 17, 64 6 7 8 9 10 11 14 15 18 19 20 21 22 23 to 26, 39, 42 to 45, 58 27, 30 to 38 28, 40, 53 29, 41, 52 46 to 51, 54 to 57 59 60 61 62 63 Mnemonic AGND VIN+_A VIN-_A AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B VIN-_B VIN+_B CLK_B DCS DFS PDWN_B OEB_B DNC D0_B (LSB) to D9_B (MSB) DRGND DRVDD D0_A (LSB) to D9_A (MSB) OEB_A PDWN_A MUX_SELECT SHARED_REF CLK_A Description Analog Ground. Analog Input Pin (+) for Channel A. Analog Input Pin (-) for Channel A. Analog Power Supply. Differential Reference (+) for Channel A. Differential Reference (-) for Channel A. Voltage Reference Input/Output. Reference Mode Selection. Differential Reference (-) for Channel B. Differential Reference (+) for Channel B. Analog Input Pin (-) for Channel B. Analog Input Pin (+) for Channel B. Clock Input Pin for Channel B. Duty Cycle Stabilizer (DCS) Mode Pin (Active High). Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement). Power-Down Function Selection for Channel B (Active High). Output Enable for Channel B (Low Setting Enables Channel B Output Data Bus). Outputs are high impedance when OEB_B is set high. Do Not Connect Pins. Should be left floating. Channel B Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 F capacitor. Recommended decoupling is 0.1 F capacitor in parallel with 10 F. Channel A Data Output Bits. Output Enable for Channel A (Low Setting Enables Channel A Output Data Bus). Outputs are high impedance when OEB_A is set high. Power-Down Function Selection for Channel A (Active High). Data Multiplexed Mode. (See Data Format section for how to enable). Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). Clock Input Pin for Channel A.
Rev. 0 | Page 11 of 36
AD9216 TERMINOLOGY
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing tEH in the Clock Input and Considerations section. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 and by taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) The ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input)
SINAD MEASURED - 1.76 dB ENOB = 6.02
Full-Scale Input Power Expressed in dBm and computed using the following equation.
V 2 FULLSCALE rms Z INPUT PowerFULLSCALE = 10 log 0.001

Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a 50% crossing of the CLK rising edge and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) This value includes both thermal and quantization noise.
- SNRdBc - SignaldBFS FS Vnoise = Z x 0.001 x 10 dBm 10 where:
Z is the input impedance.

FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale.
Rev. 0 | Page 12 of 36
AD9216
Power Supply Rejection Ratio The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first seven harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Rev. 0 | Page 13 of 36
AD9216 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD = 3.0 V, T = 25C, AIN differential drive, full scale = 2 V mode, internal reference, DCS on, unless otherwise noted.
0 SNR = 57.8dB SINAD = 57.8dB H2 = -92.7dBc H3 = -80.3dBc SFDR = 78.2dBc
AMPLITUDE (dBFS)
0 -10 -20 -30 -40 -50 -60 -70 -80
04775-018
-20
70MHz ON CHANNEL A ACTIVE
AMPLITUDE (dBFS)
-40
-60
76MHz CROSSTALK FROM CHANNEL B
-80
-100
-90 -100 27
-120 0 10 20 30 40 50 FREQUENCY (MHz)
28
29 (76)
30
31
32
33
34
FREQUENCY (MHz)
35 (70)
36
Figure 4. FFT: fS = 105 MSPS, AIN = 10.3 MHz @ -0.5 dBFS
Figure 7. FFT: fS = 105 MSPS, AIN =70 MHz, 76 MHz (A Port FFT while Both A and B Ports Are Driven @ -0.5 dBFS)
100
0 SNR = 56.9dB SINAD = 56.8dB H2 = -78.5dBc H3 = -80dBc SFDR = 78.3dBc
H3 90 H2 80
-20
AMPLITUDE (dBFS)
-40
-60
dB
70
-80
SFDR SNR 60
04775-019
04775-022
-100
SINAD 50 0 20 40 60 80 100 120 CLOCK FREQUENCY (MHz)
-120 0 10 20 30 40 50 FREQUENCY (MHz)
Figure 5. FFT: fS = 105 MSPS, AIN = 70 MHz @ -0.5 dBFS
0 SNR = 57.5dB SINAD = 57.3dB H2 = -74dBc H3 = -84.3dBc SFDR = 74dBc
100
Figure 8. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ -0.5 dBFS
-20
90 H2 80 H3
AMPLITUDE (dBFS)
-40
dB
-60
70
-80
60
SFDR SNR
04775-023
-100
04775-020
-120 0 10 20 30 40 50 FREQUENCY (MHz)
50 0 50 100 150
SINAD 200 250
300
ANALOG INPUT FREQUENCY (MHz)
Figure 6. FFT: fS = 105 MSPS, AIN = 100 MHz @ -0.5 dBFS
Figure 9. Analog Input Frequency Sweep, AIN =-0.5 dBFS, fS = 105 MSPS
Rev. 0 | Page 14 of 36
04775-021
AD9216
80
100 90
70 SFDR dBFS 60
80 70 60 TWO-TONE SFDR dBFS TWO-TONE SFDR dBc
dB
dB
65dB REF LINE
50 SFDR dBc 40
50 40 30 70dB REF LINE 20
30
04775-024
10 0 -60
20 -50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
-50
-40
-30
-20
-10
0
AIN INPUT LEVEL (dBFS)
TWO-TONE ANALOG INPUT LEVEL (dBFS)
Figure 10. SFDR vs. Analog Input Level, AIN = 70 MHz, fS = 105 MSPS
0 -10 -20
Figure 13. Two-Tone Intermodulation Distortion vs. Input Drive Level (100.1 MHz and 101.1 MHz; fS = 105 MSPS; F1, F2 Levels Equal)
100 90 80 70
CURRENT (mA)
AMPLITUDE (dBFS)
-30 -40 -50 -60 -70 -80
04775-025
AVDD CURRENT 60 50 40 30 DRVDD CURRENT 20 10 0 0 20 40 60 80 100 SAMPLE CLOCK RATE (MSPS)
04775-028
IMD = -69.9dBc
-90 -100 0 10 20 30 40 50 INPUT FREQUENCY (MHz)
120
Figure 11. Two-Tone IMD Performance, F1, F2 = 69.1 MHz, 70.1 MHz @ -7 dBFS, 105 MSPS
90 80
Figure 14. IAVDD, IDRVDD vs. Clock Frequency, CLOAD = 5 pF, AIN = 70 MHz @ -0.5 dBFS
80
70
70 TWO-TONE SFDR dBFS 60 TWO-TONE SFDR dBc 50
SFDR DCS ON SFDR DCS OFF
60 SNR DCS ON 50
dB
70dB REF LINE 40 30 20
dB
40
SNR DCS OFF
30
04775-026
10 0 -60
20 25 30 35 40 45 50 55 60 65 70 POSITIVE DUTY CYCLE (%)
-50
-40
-30
-20
-10
0
75
TWO-TONE ANALOG INPUT LEVEL (dBFS)
Figure 12. Two-Tone Intermodulation Distortion vs. Input Drive Level (69.1 MHz and 70.1 MHz; fS = 105 MSPS; F1, F2 Levels Equal)
Figure 15. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled; AIN = 70 MHz @ -0.5 dBFS, 105 MSPS
Rev. 0 | Page 15 of 36
04775-029
04775-027
AD9216
80 75 70 65
dB 80
SFDR
75 SFDR
70 dB
60 SNR 55 50
65
60
04775-030
SINAD 55 -40 -20 0 20 40 60 80
40 0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.25
VREF (V)
TEMPERATURE (C)
Figure 16. SNR, SFDR vs. External VREF (Full Scale = 2 x VREF) AIN = 70.3 MHz @ -0.5 dBFS, 105 MSPS
1.0 0.8 0.6 GAIN ERROR (% Full Scale) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40
04775-031
Figure 19. SNR, SINAD, SFDR vs. Temperature, AIN = 70 MHz @ -0.5 dBFS, 105 MSPS (fS = 2 V, External Reference Mode)
80
75
SFDR
EXTERNAL REFERENCE MODE dB
70
65
INTERNAL REFERENCE MODE
60
SNR
04775-034
-20
0
20
40
60
80
55 2.8
SINAD 2.9 3.0 AVDD (V) 3.1
3.2
TEMPERATURE (C)
Figure 17. Typical Gain Error Variation vs. Temperature, AIN = 70 MHz @ 0.5 dBFS, 105 MSPS (Normalized to 25C)
80
Figure 20. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz @ -0.5 dBFS, 105 MSPS
2.0 1.5
75 SFDR 70 dB LSB
1.0 0.5 0 -0.5 -1.0
65
60
SNR
04775-032
SINAD 55 -40 -20 0 20 40 60 80
-2.0 0 200 400 CODE 600 800 1000
TEMPERATURE (C)
Figure 18. SNR, SINAD, SFDR vs. Temperature, AIN = 70 MHz @ -0.5 dBFS, 105 MSPS (fS = 2 V, Internal Reference Mode)
Figure 21. Typical DNL Plot, AIN = 10.3 MHz @ -0.5 dBFS, 105 MSPS
Rev. 0 | Page 16 of 36
04775-035
-1.5
04775-033
45
SNR
AD9216
2.0
4.9
1.5
4.7
1.0
4.5
0.5 TPD (ns)
LSB
4.3 4.1
0 -0.5 -1.0
04775-036
3.9 3.7 3.5 -40
-1.5 -2.0 0 200 400 CODE 600 800 1000
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 22. Typical INL Plot, AIN = 10.3 MHz @ -0.5 dBFS, 105 MSPS
Figure 23. Typical Propagation Delay vs. Temperature
Rev. 0 | Page 17 of 36
04775-037
AD9216 EQUIVALENT CIRCUITS
AVDD
AVDD
VIN+_A, VIN-_A, VIN+_B, VIN-_B
PDWN 30k
04775-004
04775-006
Figure 24. Equivalent Analog Input
AVDD
Figure 26. Power-Down Input
DRVDD
CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF
04775-005
Figure 25. Equivalent Clock, Digital Inputs Circuit
Figure 27. Digital Outputs
Rev. 0 | Page 18 of 36
04775-007
AD9216 THEORY OF OPERATION
The AD9216 consists of two high performance ADCs that are based on the AD9215 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a sample-and-hold amplifier, followed by seven 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 10-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage's input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or singleended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. input; therefore, the precise values are dependant on the application. In IF under-sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.
H
T 0.5pF VIN+ CPAR
T
T 0.5pF VIN- CPAR T
04775-008
H
Figure 28. Switched-Capacitor Input
An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:
REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF
ANALOG INPUT
The analog input to the AD9216 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance. The SHA input is a differential switched-capacitor circuit. In Figure 28, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC's
It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as
VCMMIN = VREF/2 VCMMAX = (AVDD + VREF)/2
The minimum common-mode input level allows the AD9216 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a singleended source may be driven into VIN+ or VIN-. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN-.
Rev. 0 | Page 19 of 36
AD9216
The AD9216 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.
85 80 2V p-p SFDR 75 70 65
1.3k 523 49.9 499 499 33 AVDD VIN+
For dc-coupled applications, the AD8138, AD8139, or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 31 shows an example with the AD8138. The AD9216 PCB has an optional AD8351 on board, as shown in Figure 38 and Figure 39. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.
AD8138
20pF 33
AD9216
VIN-
04775-011
dB
60 2V p-p SNR 55 50 45 40 0.25
04775-009
0.1F
2k
499
AGND
Figure 31. Driving the ADC with the AD8138
SENSE = GROUND
0.75 1.25 1.75 2.25 ANALOG INPUT COMMON-MODE VOLTAGE (V)
2.75
Figure 29. Input Common-Mode Voltage Sensitivity
Differential Input Configurations
As previously detailed, optimum performance is achieved while driving the AD9216 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9216. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 30.
AVDD VIN_A 2V p-p 49.9 10pF 50 VIN_B 10pF 1k 0.1F 1k AGND
VIN+
FULL SCALE/2
AVDD/2
AVDD/2
VIN-
Figure 32. Analog Input Full Scale (Full Scale = 2 V)
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance.
50
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9216 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9216's separate clock inputs allow for clock timing skew (typically 1 ns) between the channels without significant performance degradation.
AD9216
Figure 30. Differential Transformer Coupling
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.
04775-010
Rev. 0 | Page 20 of 36
04775-012
DIGITAL OUT = ALL ONES
DIGITAL OUT = ALL ZEROES
AD9216
The AD9216 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. Faster input clock rates (where it becomes difficult to maintain 50% duty cycles) can benefit from using DCS as a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by tying the DCS pin high. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 s to 3 s to allow the DLL to acquire and settle to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by
SNR degradation = 2 x log 10[1/2 x p x fINPUT x tJ]
The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. Either channel of the AD9216 can be placed into standby mode independently by asserting the PWDN_A or PDWN_B pins. Time to go into or come out of standby mode is 5 cycles maximum when only one channel is being powered down. When both channels are powered down, VREF goes to ground, resulting in a wake-up time of ~7 mS dependent on decoupling capacitor values. It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 3 mW for the ADC. If the clock inputs remain active while in total standby mode, typical power dissipation of 10 mW results. The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles.
In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Under-sampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9216, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9216 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
DIGITAL OUTPUTS
The AD9216 output drivers can interface directly with 3 V logic families. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches because large drive currents tend to cause current glitches on the supplies that may affect converter performance. The data format can be selected for either offset binary or twos complement. This is discussed in the Data Format section.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by
IDRVDD = VDRVDD x CLOAD x fCLOCK x N
where N is the number of bits changing, and CLOAD is the average load on the digital pins that changed.
Rev. 0 | Page 21 of 36
AD9216
OUTPUT CODING
Table 8.
Code 1023 1023 1022 * * 513 512 511 * * 1 0 0 (VIN+) - (VIN-) > +0.998 V +0.998 V +0.996 V * * +0.002 V +0.0 V -0.002 V * * -0.998 V -1.000 V < -1.000 V Offset Binary 11 1111 1111 11 1111 1111 11 1111 1110 * * 10 0000 0001 10 0000 0000 01 1111 1111 * * 00 0000 0001 00 0000 0000 00 0000 0000 Twos Complement 01 1111 1111 01 1111 1111 01 1111 1110 * * 00 0000 0001 00 0000 0000 11 1111 1111 * * 10 0000 0001 10 0000 0000 10 0000 0000
DATA FORMAT
The AD9216 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement. The output data from the dual ADCs can be multiplexed onto a single 10-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, i.e., the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports. If the ADCs are run with synchronized timing, this same clock can be applied to the MUX_SELECT bit. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel's data is placed on the bus. Typically, the other unused bus is disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 33 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel's power-down pin must remain low.
TIMING
The AD9216 provides latched data outputs with a pipeline delay of six clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9216. These transients can detract from the converter's dynamic performance. The lowest conversion rate of the AD9216 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade.
A-1
A0
A1
A2
A8 A3 A4 A5 A7 A6
ANALOG INPUT ADC A
B-1
B0
B1
B2
B8 B3 B4 B5 B7 B6
ANALOG INPUT ADC B
CLK_A = CLK_B = MUX_SELECT
B-7
A-6
B-6
A-5
B-5
A-4
B-4
A-3
B-3
A-2
B-2
A-1
B-1
A0
B0
A1
B1
D0_A -D11_A
Figure 33. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. 0 | Page 22 of 36
04775-013
AD9216
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the AD9216. The input range can be adjusted by varying the reference voltage applied to the AD9216, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). Note that optimum performance is obtained with VREF = 1.0 V; performance degrades as VREF (and full scale) reduces (see Figure 16). In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+ VIN- REFT 0.1F ADC CORE 0.1F REFB 0.1F VREF 10F 0.1F SENSE SELECT LOGIC 0.5V 10F
Internal Reference Connection
A comparator within the AD9216 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 34), setting VREF to 1 V. If a resistor divider is connected, as shown in Figure 35, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
VREF = 0.5 x (1 + R2/R1)
AD9216
Figure 34. Internal Reference Configuration
Table 9. Reference Configuration Summary
Selected Mode External Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 x (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 x External Reference 2 x VREF (See Figure 35) 2.0
Rev. 0 | Page 23 of 36
04775-014
AD9216
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 36 shows the typical drift characteristics of the internal reference. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9216 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 37 depicts how the internal reference voltage is affected by loading.
VIN+ VIN- REFT 0.1F ADC CORE 0.1F REFB 0.1F VREF 10F 10F SENSE R1 R2 SELECT LOGIC 0.5V 10F
0.6
0.5
VREF ERROR (%)
0.4
0.3 VREF = 1.0V 0.2
0.1
04775-016
0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 36. Typical VREF Drift
0.05
0
VREF ERROR (%)
-0.05
-0.10 VREF = 1.0V -0.15
-0.20
04775-017
-0.25 0 0.5 1.0 1.5 ILOAD (mA) 2.0 2.5 3.0
Figure 37. VREF Accuracy vs. Load
Shared Reference Mode
The shared reference mode allows the user to connect the references from the dual ADCs together externally for superior gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high, and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.)
04775-015
AD9216
Figure 35. Programmable Reference Configuration
Rev. 0 | Page 24 of 36
AD9216 DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI's standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI's ADC AnalyzerTM software allows for quick ADC evaluation.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional AD8139 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
POWER CONNECTOR
Power is supplied to the board via three detachable 4-lead power strips.
Table 10. Power Connector
Terminal VCC1 3.0 V VDD1 3.0 V VDL1 3.0 V VREF +5 V -5 V
1
CLOCK
The clock inputs are buffered on the board at U5 and U6. These gates provide buffered clocks to the on-board latches U2 and U4, ADC input clocks, and DRA, DRB that are available at the output connector P3, P8. The clocks can be inverted at the timing jumpers labeled with the respective clocks. The clock paths also provide for various termination options. The ADC input clocks can be set to bypass the buffers at P2 to P9 and P10, P12. An optional clock buffer U3, U7 can also be placed. The clock inputs can be bridged at TIEA, TIEB (R20, R40) to allow one to clock both channels from one clock source.
Table 11. Jumpers
Terminal OEB A PWDN A MUX SHARED REF DR A LATA ENC A OEB B PWDN B DFS SHARED REF DR B LATB ENC B Comments Output Enable for A Side Power-Down A Mux Input Shared Reference Input Invert DR A Invert A Latch Clock Invert Encode A Output Enable for B Side Power-Down B Data Format Select Shared Reference Input Invert DR B Invert B Latch Clock Invert Encode B
Comments Analog supply for ADC Output supply for ADC Supply circuitry Optional external VREF Optional op amp supply Optional op amp supply
VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective primary side transformer. T1 and T2 are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the secondary transformer to reduce high frequency aliasing.
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal reference mode is selected by placing a jumper from E41 to ground (E27). External reference mode is selected by placing a jumper from E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are latched on the PCB at U2, U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance.
Rev. 0 | Page 25 of 36
AD9216
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12.
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Quantity 2 7 44 6 2 6 3 3 2 4 10 4 9 6 2 27 4 2 1 8 2 1 2 2 2 2 Reference Designator C1, C3 C2, C5, C7, C9, C10, C22, C36 C4, C6, C8, C11 to C15, C20, C21, C24 to C27, C29 to C35, C39 to C61 C16 to C19, C37, C38 C23, C28 J1 to J6 P1, P4, P11 P1, P4, P11 P31, P8 R1, R2, R32, R34 R3, R6, R7, R8, R11, R14, R33, R42, R51, R61 R4, R5, R36, R37 R9, R10, R12, R13, R20, R35, R38, R40, R43 R15, R16, R18, R26, R29, R31 R17, R25 R19, R21, R27, R28, R39, R41, R44, R46 to R49, R52, R54, R55, R5 to R60, R62 to R70 R22 to R24, R30 R45, R56 R50 RZ1 to RZ6, RZ9, RZ10 T1, T2 U1 U2, U425 U32, U7 U5, U6 U11, U12 Device Capacitors Capacitors Capacitors
Preliminary Technical Data
Package 0201 0805 0402 TAJD 0201 Z5.531.3425.0 25.602.5453.0 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 AWT-1WT LFCSP-64 TSSOP-48 SOT-70 SO-14 SO-8/EP
Value 20 pF 10 F 0.1 F 10 F 0.1 F Wieland Wieland 36 50 33 0 499 525 1000 40 10 k 22 220 Mini-Circuits
Capacitors Capacitors SMBs Power Connector Posts Detachable Connectors Connectors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Resistor Pack Transformers AD9216 SN74LVTH162374 SN74LVC1G0 SN74VCX86 AD8139
1 2
P3, P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA. U3, U7 not placed.
Rev. 0 | Page 26 of 36
VD VD R33 100 ENCA
C25 0.1F
DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED
C58 C36 0.1F 10F
R64 1k E7 MUX J6 R61 50 R43 U7
VD
E9 0 VD R42 100 VD E17 P10 P12 74LCX86 E10
C56 0.1F
P11 1 VD E5 R63 1k E18 E20 VDD ENCODE A
C40 0.1F R41 1k P14 E3 R44 1k VD E4 C8 0.1F J3 R39 1k TIEA
P4 P1 3 -5V VD E6 4 1 2 3 4
R65 1k
SN74LVC1G04 5 1 NC VCC 2 A 3 4 Y GND
1
2
3
4
2
LFCSP PCB SCHEMATICS
VD +5V R66 1k
C44 C45 -5V VD +5V VDD VDL EXT_VREF
VDD
VDL EXT_VREF
E13 E12
VD
P5 P6 P7 VD
C39 C43
VD VDD VDL ENCA
C37 C38
+ VD OTRA D13A D12A D11A D10A D9A D8A D7A
0.1F 0.1F 0.1F 0.1F R11 50
C16 C17 C18
+
+
+
C19
+
R62 1k
R46 1k E14 E15 R47 1k U6
Preliminary Technical Data
VD
H3 MTHOLE6 H1 MTHOLE6 H2 MTHOLE6
10F
H4 MTHOLE6 65 R4 33 AMPOUTA
C1 20pF C23 0.1F
C14 R3 50 0.1F T2 R5 33
C24 0.1F
AIN A 2 3 6 5 CTAPA 4
AMPINA
EPAD AVDD5 CLK_A SH_REF MUX_SEL PWDN_A OEB_A OTR_A D13_A D12_A D11_A D10_A DRGND2 DRVDD2 D9_A D8_A D7_A
J4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
C31 0.1F
CTAPA 1
C9 10F R57 1k R59 1k C10 10F C12 0.1F
C13 R7 50 0.1F AMPOUTB
T1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
J1 R36 33
AVDD3 CLK_B DCS DFS PDWN_B OEB_B D0_B D1_B D2_B D3_B D4_B DRGND DRVDD D5_B D6_B D7_B
AIN B
VD 6 C5 C55 REFT_A C26 7 REFB_A 10F 0.1F AMPOUTAB 0.1F R58 8 PADS TO SHORT VREF VREF SEE 1k REFERENCES TOGETHER 9 C29 BELOW SENSE SENSE 0.1F REFTA P15 E43 VD REFB_B 10 REFTB C7 C54 REFB_B P16 E42 VD REFT_B 11 REFBA C27 REFT_B 10F 0.1F 0.1F P18 12 REFBB R60 VD AVDD2 P17 C28 1k 13 0.1F AGND2 CTAPB AMPOUTBB 14 VIN_BB 1 6 15 R37 VIN_B CTAPB 2 5 C3 33 16 AGND3 AMPINB 20pF 3 4
D0B D1B D2B D3B D4B
D5B D6B D7B
VREF AND SENSE CIRCUIT
VD ENCB
VD E27 E41 E30 E2 R45 10k C30 0.1F VREF C2 10F
EXT_VREF
AD9216
04775-038
+
10F 10F 10F 10F 10F
1 2 3 4 5 6 7 1A VCC 4B 1B 4A 1Y 4Y 2A 3B 2B 3A 2Y GND 3Y
14 VD 13 12 11 0 10 R10 DRA 9 8 0 R9 CLKLATA
TO TIE CLOCKS TOGETHER 0 C4 0.1F J5 VDD R14 50 R35 R38 0 0 R20 0 R40 MUX
1 2 3 4 5 AGND VIN_A VIN_AB AGND1 AVDD1
D6A D5A D4A D3A D2A D1A D0A
U1
48 47 46 45 44 43 42 41 40
TIEA TIEB
Figure 38. PCB Schematic (1 of 3)
Rev. 0 | Page 27 of 36
39 38 37 36 35 34 D8_B 33 0.1F VDD C6
J2 ENCODE B R51 50 R54 1k TIEB R52 1k C42 0.1F
D6_A D5_A D4_A D3_A D2_A D1_A D0_A DRVDD1 DRGND1 OTR_B D13_B D12_B D11_B D10_B D9_B
OTRB D13B D12B D11B D10B D9B SN74LVC1G04 D8B 1 5 NC VCC
2 A 3 GND Y 4
C57 C22 0.1F 10F
DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED VD 22 VD U3
VD
R50 R8 100 P2 P9 P13
VD E35 R49 1k E36
R6 100 ENCB
U5 0 R12 0 R68 1k R70 1k R13 R69 1k VD CLKLATB E34 E16 VD DRB R48 1k E37 E38
R56 10k E25 SENSE
C11 0.1F
8 9 10 11 12 13 14 R67 1k E24 VD E40 E22 E29 E21 VD VD E26 E33 VD E31 C41 0.1F
3Y GND 2Y 3A 2B 3B 2A 4Y 1Y 4A 1B 4B VCC 1A 74LCX86
7 6 5 4 3 2 1
VD R55 1k
AD9216
CLKLATA
39 39
OTRA D13A D12A D11A D10A D9A D8A D7A VDL P3
RZ3 220 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 RZ5 220 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 DORP D13P D12P D11P D10P D9P D8P D7P
D6A D5A D4A D3A D2A D1A D0A VDL D6P D5P D4P D3P D2P D1P D0P SN74LVCH16373A U2 RZ10 220 RSO16ISO CLKLATB
RZ4 220 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9
25 26 27 28 29 30 VDL 31 32 33 34 35 36 37 38 39 40 41 VDL 42 43 44 45 46 47 CLKLATA 48 RZ6 220 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 HEADER40 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DRA GND D13P D12P D11P D10P D9P D8P D7P D6P D5P D4P D3P D2P D1P D0P DORP
Q = OUTPUT LE2 D = INPUT OE2 2D8 2Q8 2D7 2Q7 GND GND 2D6 2Q6 2D5 2Q5 VCC VCC 2D4 2Q4 2D3 2Q3 GND GND 2D2 2Q2 2D1 2Q1 1D8 1Q8 1D7 1Q7 GND GND 1D6 1Q6 1D5 1Q5 VCC VCC 1D4 1Q4 1D3 1Q3 GND GND 1D2 1Q2 1D1 1Q1 OE1 LE1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 39. PCB Schematic (2 of 3)
VDL
Rev. 0 | Page 28 of 36
OTRB D13B D12B D11B D10B D9B D8B D7B RZ9 220 RSO16ISO 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 D6B D5B D4B D3B D2B D1B D0B SN74LVCH16373A U4 VDL C49 C48 C47 C46 C53 C52 C51 C50 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 220 RZ2 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 VDL 25 26 27 28 29 30 VDL 31 32 33 34 35 36 37 38 39 40 41 VDL 42 43 44 45 46 47 CLKLATB 48 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 Q = OUTPUT LE2 D = INPUT OE2 2D8 2Q8 2D7 2Q7 GND GND 2D6 2Q6 2D5 2Q5 VCC VCC 2D4 2Q4 2D3 2Q3 GND GND 2D2 2Q2 2D1 2Q1 1D8 1Q8 1D7 1Q7 GND GND 1D6 1Q6 1D5 1Q5 VCC VCC 1D4 1Q4 1D3 1Q3 GND GND 1D2 1Q2 1D1 1Q1 OE1 LE1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D6Q D5Q D4Q D3Q D2Q D1Q D0Q
04775-039
RZ1 220 RSO16ISO 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9
DORQ D13Q D12Q D11Q D10Q D9Q D8Q D7Q
39
39
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
P8
37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 HEADER40
37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
DRB GND D13Q D12Q D11Q D10Q D9Q D8Q D7Q D6Q D5Q D4Q D3Q D2Q D1Q D0Q DORQ
Preliminary Technical Data
Preliminary Technical Data
OP AMP INPUT OFF PIN ONE OF TRANSFORMER AMPINB AMPINA
R29 499 R25 525 R17 525 VD R28 1k R26 499 C20 C15 C60 8 C33 0.1F -5V 7 6 5 +IN NC V- -OUT 0.1F R15 499
R16 499 VD R19 1k
C61 C34 0.1F 8 +IN -IN 2 3 4 +5V C35 0.1F U12 R24 40 AMPOUTB AMPOUTBB R30 40 V+ +OUT NC V- -OUT VOCM EPAD 7 6 -5V 5 1
9 R27 1k
9 EPAD -IN VOCM V+ +OUT 1 2 3 4
Figure 40. PCB Schematic (3 of 3)
Rev. 0 | Page 29 of 36
AD8139
R31 499
R21 1k
C21 0.1F R18 499 +5V
C59
AD8139
U11 R23 40 AMPOUTAB R22 40 AMPOUTA
C32 0.1F
04775-040
AD9216
AD9216
LFCSP PCB LAYERS
Preliminary Technical Data
Figure 41. PCB Top-Side Silkscreen
Rev. 0 | Page 30 of 36
04775-041
Preliminary Technical Data
AD9216
Figure 42. PCB Top-Side Copper Routing
Rev. 0 | Page 31 of 36
04775-042
AD9216
Preliminary Technical Data
Figure 43. PCB Ground Layer
Rev. 0 | Page 32 of 36
04775-043
Preliminary Technical Data
AD9216
Figure 44. PCB Split Power Plane
Rev. 0 | Page 33 of 36
04775-044
AD9216
Preliminary Technical Data
Figure 45. PCB Bottom-Side Copper Routing
Rev. 0 | Page 34 of 36
04775-045
Preliminary Technical Data
AD9216
Figure 46. PCB Bottom-Side Silkscreen
THERMAL CONSIDERATIONS
The AD9216 LFCSP package has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. Improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. Recommended array is 0.3 mm vias on 1.2 mm pitch. JA = 26.4C/W with this recommended configuration. Soldering the slug to the PCB is a requirement for this package.
Figure 47. Thermal Via Array
04775-046
Rev. 0 | Page 35 of 36
04775-047
AD9216 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
Preliminary Technical Data
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.85 4.70 SQ* 4.55
0.45 0.40 0.35
33 32
16 17
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
7.50 REF
SEATING PLANE
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION
Figure 48. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body (CP-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9216BCPZ-1051 AD9216BCPZRL7-1051 AD9216-105PCB Temperature Range -40C to +85C -40C to +85C Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP) 64-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board with AD9216BCPZ-105 Package Option CP-64-1 CP-64-1
1
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04775-0-10/04(0)
Rev. 0 | Page 36 of 36
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